A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

Author

Ohbayashi, Shigeki ; Yabuuchi, Makoto ; Kono, Kazuhi ; Oda, Yuji ; Imaoka, Susum ; Usui, Keiichi ; Yonezu, Toshiaki ; Iwamoto, Takeshi ; Nii, Koji ; Tsukamoto, Yasumasa ; Arakawa, Masashi ; Uchida, Takahiro ; Okada, Masakazu ; Ishii, Atsushi ; Makino, Hir

Author_Institution

Renesas Technol., Itami

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

488

Lastpage

617

Abstract

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

Keywords

SRAM chips; low-power electronics; redundancy; system-on-chip; 16 Mbit; 50 ps; 65 nm; e-trim fuse; electrically trimmable fuse; embedded SRAM; known good die SoC; leak-bit redundancy; low-standby-power technology; repair scheme; wafer-level burn-in mode; Bismuth; CMOS technology; Circuit testing; Costs; Electronics packaging; Fuses; Latches; Random access memory; Temperature; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373507

Filename

4242478