DocumentCode
2870731
Title
A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
Author
Haraguchi, Masaru ; Osawa, Tokuya ; Yamazaki, Akira ; Morishima, Chikayoshi ; Morihara, Toshinori ; Morooka, Yoshikazu ; Okuno, Yoshihiro ; Arimoto, Kazutami
Author_Institution
Renesas Technol., Itami
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
490
Lastpage
491
Abstract
An experimental chip for a 32b wide DDR2 SDRAM interface for SoC is fabricated in a 90nm CMOS process and achieves 960Mb/s/pin operation. Impedance-calibration circuits and flexible round-trip circuits in a continuous-adaptive DDR2 interface are used to suppress skew and allow a longer round-trip time.
Keywords
CMOS integrated circuits; DRAM chips; calibration; flexible electronics; system-on-chip; 32 bit; 90 nm; CMOS process; DDR2 SDRAM interface; SoC; continuous-adaptive DDR2 interface; flexible round-trip circuits; impedance-calibration circuits; loop-backed AC test; Automatic testing; Calibration; Circuit testing; Clocks; Delay; Frequency; Impedance; SDRAM; Table lookup; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373508
Filename
4242479
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