An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

Author

Ihm, Jeong-Don ; Bae, Seung-Jun ; Park, Kwang-Il ; Song, Ho-Young ; Lee, Woo-Jin ; Kim, Hyun-Jin ; Kim, Kyung-Ho ; Lee, Ho-Kyung ; Park, Min-Sang ; Bang, Sam-Young ; Lee, Mi-Jin ; Moon, Gil-Shin ; Jang, Young-Wook ; Hwang, Suk-Won ; Cho, Young-Chul ; Hwan

Author_Institution

Samsung Electron., Hwasung

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

492

Lastpage

617

Abstract

A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21 ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.

Keywords

DRAM chips; calibration; jitter; low-power electronics; system buses; 21 ps; 32 bit; 512 Mbit; 68 mV; 80 nm; GDDR4 graphics DRAM; auto-calibration; data-bus inversion coding scheme; driver impedance; dual duty-cycle corrector; low-noise data-bus inversion; low-power electronics; peak-to-peak jitter; termination impedance; Circuits; Clocks; Crosstalk; Detectors; Graphics; Jitter; Noise reduction; Random access memory; Shape control; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373509

Filename

4242480