• DocumentCode
    2870756
  • Title

    Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM

  • Author

    Johnson, Brian ; Keeth, Brent ; Lin, Feng ; Zheng, Hua

  • Author_Institution
    Micron Technol., Boise, ID
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    494
  • Lastpage
    617
  • Abstract
    A 512Mb graphics DRAM device uses phase-tolerant read and write latency control to achieve 2Gb/s/pin GDDR3 and 2.5G/ps/pin GDDR4 operation. The IC is implemented in a 95nm 1.5V triple metal CMOS process.
  • Keywords
    CMOS integrated circuits; DRAM chips; 1.5 V; 512 Mbit; 95 nm; DRAM device; GDDR3 SDRAM; GDDR4 SDRAM; integrated circuit implementation; phase-tolerant latency control; read and write latency control; triple metal CMOS process; Clocks; Control systems; Counting circuits; Decoding; Delay; Random access memory; Reflective binary codes; SDRAM; Synchronization; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373510
  • Filename
    4242481
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2870756