Title :
A latching comparator for 12b A/D applications
Author_Institution :
Precision Monolithics, Inc., Santa Clara, CA, USA
Abstract :
A comparator with 0.1LSB error and 50ns response time with 0.5LSB overdrive, for use in a 12b successive approximation A/D will be described. The circuit-junction isolated-includes a buried-zener level shift.
Keywords :
Capacitance; Circuits; Degradation; Delay; Dielectric devices; Diodes; Latches; Power generation; Resistors; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1980.1156135
