Title :
A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC
Author :
Snoeij, M.F. ; Donegan, P. ; Theuwissen, A.J.P. ; Makinwa, K.A.A. ; Huijsing, J.H.
Author_Institution :
Delft Univ. of Technol.
Abstract :
A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.
Keywords :
CMOS image sensors; analogue-digital conversion; comparators (circuits); 0.25 micron; CMOS image sensor; column-level ADC; digital circuitry; multiple-ramp single-slope ADC; single comparator; CMOS image sensors; Circuit testing; Clocks; Image converters; Image sensors; Prototypes; Random access memory; Resistors; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373516
