The hardware implementation of a generic fuzzy rule processor

In this paper, the hardware design and implementation of a generic fuzzy processor is described. The processor allows the user to choose from a large range of inference and defuzzification methods. The number of inputs and outputs was limited to 3, with a width of 8-bits for each. Rule base size and the number of inferences that can be performed per second were not a critical factor as larger and faster specifications will simply increase the end cost. Design and simulation using Altera´s Max+plus2 programmable logic development software was then conducted, and verified correct operation. The generic fuzzy processor was ultimately realised via construction using Altera FLEX 8000 FPGAs