DocumentCode
2872201
Title
Design methodologies for VLSI
Author
Broderson, R.
Author_Institution
University of California, Berkeley, CA, USA
Volume
XXIV
fYear
1981
fDate
18-20 Feb. 1981
Firstpage
200
Lastpage
201
Abstract
As the complexity of ICs increases at an exponential rate, the cost and time of design has similarly escalated. Among the evolving layout methods to be compared are the use of standard cells, gate arrays, high level symbolic and structured design techniques.
Keywords
Circuit testing; Costs; Design automation; Design methodology; Logic arrays; Logic design; Logic testing; Microelectronics; Technology management; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1981.1156220
Filename
1156220
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