DocumentCode
2872222
Title
A 16-DIP 64Kb static MOS RAM
Author
Wada, T. ; Yamanaka, H. ; Sakamoto, M. ; Yamamoto, H. ; Matsue, S.
Author_Institution
Nippon Electric Company, Ltd., Tokyo, Japan
Volume
XXIV
fYear
1981
fDate
18-20 Feb. 1981
Firstpage
16
Lastpage
17
Abstract
A 64K×1b fully static MOS RAM using 1.5μm design rules will be described. The device has multiplexed addressing and is assembled in a standard 300-mil 16-pin DIP.
Keywords
Circuits; Clocks; DRAM chips; Decoding; Electronics packaging; Inverters; Lithography; Power dissipation; Read-write memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1981.1156221
Filename
1156221
Link To Document