DocumentCode :
2872482
Title :
Dynamic prediction of critical path instructions
Author :
Tune, Eric ; Liang, Dongning ; Tullsen, Dean M. ; Calder, Brad
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear :
2001
fDate :
2001
Firstpage :
185
Lastpage :
195
Abstract :
Modern processors come close to executing as fast as role dependences allow. The particular dependences that constrain execution speed constitute the critical path of execution. To optimize the performance of the processor we either have to reduce the critical path or execute it more efficiently. In both cases, it can be done more effectively if we know the actual instructions that constitute that path. This paper describes critical path prediction for dynamically identifying instructions likely to be on the critical path, allowing various processor optimizations to take advantage of this information. We show several possible critical path prediction techniques and apply critical path prediction to value prediction and clustered architecture scheduling. We show that critical path prediction has the potential to increase the effectiveness of these hardware optimizations by as much as 70%, without adding greatly to their cost
Keywords :
microprocessor chips; optimisation; critical path; critical path instructions; critical path prediction; dynamic prediction; execution speed; performance optimisation; processor optimizations; processors; role dependences; Capacitive sensors; Computer science; Constraint optimization; Cost function; Hardware; Modems; Out of order; Processor scheduling; Registers; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on
Conference_Location :
Monterrey
ISSN :
1530-0897
Print_ISBN :
0-7695-1019-1
Type :
conf
DOI :
10.1109/HPCA.2001.903262
Filename :
903262
Link To Document :
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