DocumentCode
2872519
Title
DLP+TLP processors for the next generation of media workloads
Author
Corbal, Jesus ; Espasa, Roger ; Valero, Mateo
Author_Institution
Dept. d´´Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
fYear
2001
fDate
2001
Firstpage
219
Lastpage
228
Abstract
Future media workloads will require about two levels of magnitude the performance achieved by current general purpose processors. High uni-threaded performance will be needed to accomplish real-time constraints together with huge computational throughput, as next generation of media workloads will be eminently multithreaded (MPEG-4/MPEG-7). In order to fulfil the challenge of providing both good uni-threaded performance and throughput, we propose to join the simultaneous multithreading execution paradigm (SMT) together with the ability to execute media-oriented streaming μ-SIMD instructions. This paper evaluates the performance of two different aggressive SMT processors: one with conventional μ-SIMD extensions (such as MMX) and one with longer streaming vector μ-SIMD extensions. We will show that future media workloads are, in fact, dominated by the scalar performance. The combination of SMT plus streaming vector μ-SIMD helps alleviate the performance bottleneck of the integer unit. SMT allows “hiding” vector execution underneath integer execution by overlapping the two types of computation, while the streaming vector μ-SIMD reduces the pressure on issue width and fetch bandwidth, and provides a powerful mechanism to tolerate latency that allows to implement smart decoupled cache hierarchies
Keywords
microprocessor chips; multi-threading; performance evaluation; general purpose processors; media workloads; multithreading; performance; real-time constraints; simultaneous multithreading execution paradigm; smart decoupled cache hierarchies; uni-threaded performance; vector execution; Delay; High performance computing; Instruction sets; Kernel; MPEG 7 Standard; Multithreading; Streaming media; Surface-mount technology; Throughput; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on
Conference_Location
Monterrey
ISSN
1530-0897
Print_ISBN
0-7695-1019-1
Type
conf
DOI
10.1109/HPCA.2001.903265
Filename
903265
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