DocumentCode :
2872608
Title :
Reducing DRAM latencies with an integrated memory hierarchy design
Author :
Lin, Wei-Fen ; Reinhardt, Steven K. ; Burger, Doug
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., MI, USA
fYear :
2001
fDate :
2001
Firstpage :
301
Lastpage :
312
Abstract :
In this paper we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated one-megabyte level-two cache, a processor still spends over half of its time stalling for L2 misses. Large cache blocks can improve performance, but only when coupled with wide memory channels. DRAM address mappings also affect performance significantly. We evaluate an aggressive prefetch unit integrated with the L2 cache and memory, controllers. By issuing prefetches only when the Rambus channels are idle, prioritizing them to maximize DRAM row buffer hits, and giving them low replacement priority, we achieve a 43% speedup across 10 of the 26 SPEC2000 benchmarks, without degrading performance an the others. With eight Rambus channels, these ten benchmarks improve to within 10% of the performance of a perfect L2 cache
Keywords :
cache storage; memory architecture; performance evaluation; DRAM accesses; Rambus channels; benchmarks; cache blocks; integrated memory hierarchy; next-generation memory system; performance; performance gap; Banking; Clocks; Computer science; Degradation; Delay; Dynamic scheduling; Frequency; High performance computing; Prefetching; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on
Conference_Location :
Monterrey
ISSN :
1530-0897
Print_ISBN :
0-7695-1019-1
Type :
conf
DOI :
10.1109/HPCA.2001.903272
Filename :
903272
Link To Document :
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