• DocumentCode
    2872697
  • Title

    Gate underlaid transistor

  • Author

    Werner, W. ; Scheckel, B.

  • Author_Institution
    Siemens AG, Munich, Germany
  • Volume
    XXIV
  • fYear
    1981
  • fDate
    18-20 Feb. 1981
  • Firstpage
    40
  • Lastpage
    41
  • Abstract
    This report will describe a merged bipolar/JFET structure with a 50V breakdown and fTof 0.5GHz for a standard 5V digital process.
  • Keywords
    Digital integrated circuits; Electrodes; FET integrated circuits; Impedance; JFET circuits; Logic; Merging; Paper technology; Solid state circuits; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1981.1156249
  • Filename
    1156249
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2872697