500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti"

A 128-bin, 256 ns deep switched capacitor analog waveform sampling memory ASIC "Anusmriti" is designed using 500 MHz delay lock loop (DLL) in 0.7 μm mixed CMOS process for sampling and storing the randomly occurring fast exponential signals. The stored memory samples can be read and digitized subsequently at lower rate thereby relieving the need of high speed digitization. The Anusmriti ASIC is designed specifically for pulse profile analysis of fast single shot events, occurring typically in High Energy Physics, Astronomy and laser/accelerator based experiments without using high frequency sampling clocks. This design incorporates 500 MHz delay locked loop, locked using a low frequency reference clock, so as to ensure good timing accuracy of each sampling interval at all the times. The Anusmriti ASIC has input dynamic range of 2 V and input capacitance of 64 pF. This full custom ASIC has been tested for equivalent sampling rate of 500 MHz with analog serial readout at 1 MHz. The ASIC features small bin spread across the memory depth. This paper describes design approach, trade-offs and test results of the Anusmriti ASIC. This ASIC occupies a die area of 5 mm by 3.5 mm.