A Response Surface Method for Design Space Exploration and Optimization of Analog Circuits

A new design approach for analog circuit performance optimization has been proposed. We have applied some well known Design of Experiment methods to achieve optimal sizing of transistors to satisfy multiple conflicting performance requirements simultaneously. We introduce the notion of Central Composite Design and D-optimal design technique to get the simulation data for fitting quadratic and even higher order response surface models to each of the performance metrics. The circuit-sizing problem is formulated as a constrained optimization problem. The concept of Desirability Function has been used to get a feasible design space out of the global design space where all the performance constraints are satisfied and the best solution is identified by selecting the solution, having highest overall desirability. The efficiency of the proposed approach is demonstrated on designs of a two-stage Operational Amplifier and an LC Voltage Controlled Oscillator, where multiple performance objectives are optimized with respect to selected design variables.