Title :
Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine
Author_Institution :
Comput. Eng. Dept., King Fahd Univ. of Pet. & Miner., Dhahran
Abstract :
A feasibility study for implementing the AES encryption algorithm in hardware achieving 500 Gbits/s is presented. The methodology followed in the process of obtaining the solution allowed us to reach a highly regular solution that is scalable.
Keywords :
cryptography; design engineering; AES cypher decypher engine; Advanced Encryption Standard; bit rate 500 Gbit/s; design feasibility; encryption algorithm; hardware; Computer security; Cryptography; Data security; Engines; Field programmable gate arrays; Hardware; Information security; Pipeline processing; Table lookup; Throughput; AES; ASICs; High Speed Architectures; High Throughput;
Conference_Titel :
Microelectronics, 2006. ICM '06. International Conference on
Conference_Location :
Dhahran
Print_ISBN :
1-4244-0764-8
Electronic_ISBN :
1-4244-0765-6
DOI :
10.1109/ICM.2006.373299
