Electron beam technology for power semiconductor device fabrication

The adaptation of electron beam lithography and electron beam testing techniques for production of new power semiconductor devices and some of their applications are presented. An approach is developed to decrease information volume for exposition of large chips by electron beam lithography. The computer arrangement for the electron beam system and the scheme of data preparation for electron beam lithography are proposed. It is shown that the method of electron beam induced current permits one to observe the 3-dimensional image of the gate p-n junction in a SIT structure. The electron beam testing technique is developed to measure the current gain distribution in power bipolar transistor and IGBT chips