Author :
Kounalakis, Evriklis ; Sotiriou, Christos P. ; Zebilis, Vassilis
Abstract :
This work presents a post-placement, leakage recovery methodology, based on gate resizing, which supports and preserves statistical constraints, i.e. a (mean, sigma) constraint pair during leakage optimization. We exploit statistical models for delay and leakage, which utilize normal and lognormal distributions respectively. The distributions are extracted by extrapolating process, temperature and voltage data. Our leakage recovery is based on statistical wire delay bounds generated for a (sigma, mean) constraint by the TSZSA algorithm and redistributed across gates using an ILP-based slack reassignment strategy. Available gate slack is converted into reduced leakage by downsizing the relevant gates, while preserving the statistical slack assignment. Experimental results, on the IWLS 2005 benchmarks, indicate an average of over %20 leakage recovery with no timing yield loss, where similar leakage gains for a non-statistical, state of the art leakage recovery tool present an average of over %6 loss in timing yield. We also illustrate that our gate resizing algorithm exploits a delay-leakage trade off, for a fixed sigma value.
Keywords :
circuit optimisation; delays; extrapolation; integer programming; linear programming; log normal distribution; statistical analysis; ILP-based slack reassignment strategy; Post-Placement Leakage Recovery; TSZSA algorithm; extrapolating process; gate resizing algorithm; gate slack; leakage optimization; lognormal distributions; statistical constraints; statistical models; statistical slack assignment; statistical timing; statistical wire delay bounds; Delay; Integrated circuit modeling; Leakage current; Logic gates; Optimization; Wires; leakage; statistical; timing;