The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip

This paper presents the specification and designing of a Dynamic Configuration Manager for Dynamic Reconfigurable Systems-on-chip (DRSoC). The manager is compile time parameterizable to enable the modelling of different technology specific details from vendors like Xilinx, Altera or others. The manager is embedded into a simulation environment for proof of concept purposes. It is implemented in cycle accurate System C and enables system analysis considering its performance and power metrics. With that, it allows a quantification of a specific DRSoC implementation. A System C kernel extension exposes the basis of the Dynamic Reconfiguration mechanism. The manager is also designed in RTL and implemented on a Xilinx Virtex2Pro FPGA. This allows a characterization of performance and power figures and their back-annotation into the higher level System C environment, which provides a speed-up of 25 compared to RTL.