Title :
Self-testing VLSI
Author :
Heckelman, R. ; Bhavsar, D.
Author_Institution :
General Electric Co., Syracuse NY, USA
Abstract :
A library of self-testing LSI cells for both on-line and off-line testing will be described, citing a 16×16b array multiplier with 9300 CMOS transistors as an example.
Keywords :
Automatic testing; Built-in self-test; Clocks; Cost function; Hardware; Logic testing; Pipelines; Registers; System testing; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1981.1156276
