Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET

Asymmetric and independent gate features of DGMOSFETs are explored recently for nano scale applications. This paper investigates minimization of short channel effects based on the independent gate, gate-S/D under lap and asymmetric (in front and back gate oxide thickness, gate work functions and gate bias) features of DGMOSFETs. Novel analytical models for threshold voltage, threshold voltage roll-off and DIBL effects of an under lap DGMOSFET with asymmetric, independent gate features are proposed and validated with numerical simulation results. Overall, results show that gate under lap feature and asymmetry brought in DGMOSFET by proper tuning of back gate bias, back gate oxide thickness and gate work function materials add more flexibility for tuning of DGMOSFET device threshold voltage and minimizing SCEs which are not available in tied gate symmetric DGMOSFETs.