An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance

FTL improves the performance of arithmetic circuits, with a very long logic depth, while reducing the power dissipation, when compared with standard CMOS circuits. The feed through logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. As the supply voltage is scaling down, the circuit noise immunity is being reduced. In case of FTL its speed is very good but noise immunity is poor. So FTL design will not be a good choice for industrial application in deep submicron region. In this work, a new design approach is implemented using FTL concept for high performance dynamic CMOS logic with high noise immunity. A 2 input AND gate has been designed using the improved FTL technique. Further a comparison analysis has been carried out by realizing and simulating the logic circuits in 180nm technology at supply voltage of 1.8V. At 180nm technology the ANTE & Energy normalized ANTE of proposed technique improved by 2.24X & 2.57X over conventional FTL and power dissipation is reduced by 32% over conventional FTL Technique.