DocumentCode
2873147
Title
A 6K-gate CMOS gate array
Author
Kobayashi, Takehiko ; Tago, H. ; Moriya, Takehiro ; Yamamoto, Seiichi
Author_Institution
Toshiba Corporation, Kawasaki, Japan
Volume
XXV
fYear
1982
fDate
10-12 Feb. 1982
Firstpage
174
Lastpage
175
Abstract
An array, with Propagation delays well into the subnanosecond region, featuring 2μm design rules and double layer metalization, will be reported.
Keywords
CMOS technology; Clocks; Contact resistance; Etching; Integrated circuit interconnections; Inverters; Planarization; Plasma measurements; Semiconductor device measurement; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1982.1156280
Filename
1156280
Link To Document