Enhanced Redundant via Insertion with Multi-via Mechanisms

As the process technology advances, via failure is still one of the dominant defects for semiconductor manufacturing in nanometer territory. Nowadays, redundant via insertion is the typical approach to improve yield and reliability. Increasing double-via insertion rate in concurrent routing or post-routing stage is the major objective in recent academic research. However, redundant via insertion in double-via pattern is required considerably additional routing resources that limits routers to enhance the redundant via insertion rate, especially in congestion designs. This study proposes an efficient post-routing redundant via insertion approach that considers different via configurations in two-phase flow to increase total via and via1 insertion rate. Our approach is the first to combine double-via and rectangle-via patterns that overcomes the limitation of double-via insertion. Experiment results show that the proposed methodology with the multi-via mechanisms can improve the total via insertion rate from 86.9% to 92.7%, and the via1 insertion rate from 73.9% to 85.2%.