Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM

Transistor scaling and reduction in operating voltages have resulted in cosmic-ray induced soft errors becoming a major threat for reliable processor operation. With the raw device soft error rate expected to remain constant in future generations, the explosion in on-chip transistor count is expected to have a corresponding impact on overall error rate. Consequently it becomes necessary to incorporate resiliency into the pipeline data path. However, existing methods like redundant execution or error correction used in memory are non-ideal for the pipeline due to their impact on overall performance. In this paper, we propose a novel technique that exploits the characteristics of Spin Transfer Torque - Magnetic Random Access Memory (STT-MRAM) for providing protection of all storage structures in the pipeline, namely the Reorder Buffer, Issue Queue and Load-Store Queue. We identify specific periods during an application\´s runtime when the MRAM can capture a ``snapshot" of the invariant micro-architectural state and restore it later thereby reducing soft error vulnerability. We quantify the reduction in Architectural Vulnerability Factor (AVF) to be 32% on average, with a performance overhead of less than 6%. Further, we present a case where the proposed technique can be combined with existing soft error protection techniques like Instruction Duplication to further enhance system reliability.