Title :
A CMOS LSI 16 × 16 multiplier/multiplier-accumulator
Author :
Anderson, Jon ; Troutman, B. ; Allen, Ross
Author_Institution :
TRW Electronics Systems, Redondo Beach, CA, USA
Abstract :
Two 2μ CMOS LSI chips with multiply times less than 100ns, and dissipation of 150mW, will be discussed. The use of Booth´s algorithm speeds the multiplication process since the multiplier word is essentially recoded into 8 digits.
Keywords :
CMOS process; CMOS technology; Digital signal processing chips; FETs; Large scale integration; Latches; Power supplies; Satellites; Signal processing algorithms; Vehicles;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156290
