TSV-aware Scan Chain Reordering for 3D IC

Three-dimensional ICs are emerging to overcome scaling challenges in 2D ICs. Long interconnects are reduced by shorter vertical connections, called Through Silicon Vias (TSV)s. However, TSVs incur costs in area and yield. In this paper, a TSV multiplexing scheme, for scan chains and functional path, is proposed to reduce the number of TSVs. Experiments on ISCAS89 and ITC99 Benchmark circuits indicate that on an average TSV area has reduced by 8-9%, with 3.28% impact on the scan chain wire length.