Hardware-software codesign and parallel implementation of a Golomb ruler derivation engine

Author

Sotiriades, Euripides ; Dollas, Apostolos ; Athanas, Peter

Author_Institution

Dept. of Electron. & Comput. Eng., Tech. Univ. of Crete, Chania, Greece

fYear

2000

fDate

2000

Firstpage

227

Lastpage

235

Abstract

A new architecture for Golomb ruler derivation has been developed so that rulers up to 24 marks can be proven on it. In this architecture, 8-mark stubs that are derived on a personal computer are subsequently processed by the FCCM, called GE2, allowing for parallel processing of as many stubs as are the available FPGAs. Actual runs of the new design have been performed on the TOP parallel FPGA machine at Virginia Tech. This paper presents the design improvements over the original architecture, which include single FPGA implementation, hardware/software codesign, FIFO based I/O, design for parallel execution, and performance results from actual runs

Keywords

field programmable gate arrays; hardware-software codesign; mathematics computing; parallel architectures; parallel machines; performance evaluation; FIFO; FPGA; GE2; Golomb ruler derivation engine; TOP parallel machine; hardware-software codesign; parallel implementation; parallel processing; performance results; personal computer; Computer architecture; Concurrent computing; Field programmable gate arrays; Hardware; Internet; Marine vehicles; Mathematics; Microcomputers; Parallel processing; Search engines;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-7695-0871-5

Type

conf

DOI

10.1109/FPGA.2000.903410

Filename

903410