Title :
Yield model for 256K RAMs and beyond
Author_Institution :
IBM Corp., Essex Junction, VT, USA
Abstract :
An updated yield model based on visual inspection, electrical tests, bit failure maps and failure analysis will be reported. The approach has been verified for the manufacture of 64K memories. It includes yield calculations for partially good product and redundancy and provides yield estimates for 128K and 256K chips.
Keywords :
Circuit faults; DRAM chips; Data analysis; Manufacturing; Production; Redundancy; Semiconductor device measurement; Semiconductor device modeling; Testing; Time measurement;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156326
