Gate Sizing Minimizing Delay and Area

In this work we present a gate sizing tool based on Geometric Programming. The optimization can be done targeting both, delay and power minimization. In order to qualify our approach, the ISCAS´85 benchmark circuits are mapped for 45nm technologies using standard cell library. Next, the mapped circuit is sized using our tool and the result is compared to the original mapped circuit. Speed increases 21%, on average, by delay minimization, keeping the same area and power values of the sizing provided by standard-cells library. For area optimization, where the delay was restricted to the delay value found at delay minimization, the reduction was 28.2% in area and 27.3% in power consumption, on average.