• DocumentCode
    2873972
  • Title

    A 64b floating point processor

  • Author

    Ware, F.

  • Author_Institution
    Hewlett-Packard Co., Cupertino, CA, USA
  • Volume
    XXV
  • fYear
    1982
  • fDate
    10-12 Feb. 1982
  • Firstpage
    24
  • Lastpage
    25
  • Abstract
    A floating point chip set capable of one-million scalar operations per second will be reported. The set consists of add/subtract, multiply and divide chips.
  • Keywords
    CMOS logic circuits; CMOS process; Clocks; Data buses; Logic design; Microcomputers; Pins; Process design; Propagation delay; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1982.1156327
  • Filename
    1156327
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2873972