Title :
The history and use of pipelining computer architecture: MIPS pipelining implementation
Author :
Pantazi-Mytarelli, Iro
Author_Institution :
New York Inst. of Technol., Old Westbury, NY, USA
Abstract :
Pipelining is an implementation technique whereby multiple instructions are overlapped in execution; it takes the advantage of parallelism that exists among the actions needed to execute an instruction. Today, pipelining is the key implementation technique used to make fast CPUs. However, most of the times, there are data dependencies that create problems during the execution and need to be solved. In this paper, we implemented pipelining in MIPS architecture and we observed the way that data dependencies were handled by our system.
Keywords :
instruction sets; parallel processing; pipeline processing; reduced instruction set computing; CPU; MIPS architecture; MIPS pipelining implementation; data dependency; instruction execution; multiple instructions; parallelism; pipelining computer architecture; Computer architecture; Delays; Hardware; Hazards; Pipeline processing; Reduced instruction set computing; Registers;
Conference_Titel :
Systems, Applications and Technology Conference (LISAT), 2013 IEEE Long Island
Conference_Location :
Farmingdale, NY
Print_ISBN :
978-1-4673-6244-3
DOI :
10.1109/LISAT.2013.6578243