• DocumentCode
    2873995
  • Title

    Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family

  • Author

    Chen, Chia-I ; Huang, Juinn-Dar

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2011
  • fDate
    4-6 July 2011
  • Firstpage
    369
  • Lastpage
    370
  • Abstract
    In this work, we thoroughly investigate all existing woks about distributed register-file micro architecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.
  • Keywords
    integrated circuit interconnections; memory architecture; architectural synthesis frameworks; distributed register-file microarchitecture family; variant inter-island delay models; Art; Computer architecture; Delay; Integrated circuit interconnections; Microarchitecture; Minimization; System performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Chennai
  • ISSN
    2159-3469
  • Print_ISBN
    978-1-4577-0803-9
  • Electronic_ISBN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2011.19
  • Filename
    5992528
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2873995