Title :
Reconfigurable array media processor (RAMP)
Author :
Rath, Kamlesh ; Tangirala, Sirisha ; Friel, Patrick ; Balsara, Poras ; Flores, Jose ; Wadley, John
Author_Institution :
Texas Univ., Dallas, TX, USA
Abstract :
This paper presents the architecture of a Reconfigurable Array Media Processor (RAMP). RAMP features a 2D array of coarse-grained configurable logic blocks (CLBs) connected together by local and global inter-connects. The CLBs on RAMP provide a 4-bit ALU, 2×2 bit parallel multiply function, 4-bit barrel shifter, two 4-bit registers and a local programmable control unit. RAMP is capable of partial run-time reconfiguration and supports block-mode reconfiguration. The novel features of this device include two programmable high-speed clocks available to each CLB, scalable parallel multiplier, on-chip memory/registers. RAMP can be used to implement high-performance computational kernals of video, audio and signal processing functions. Matrix multiplication, FIR filters and Inverse DCT functions are used as examples to demonstrate the capabilities of the RAMP architecture
Keywords :
FIR filters; digital arithmetic; discrete cosine transforms; matrix multiplication; microprocessor chips; reconfigurable architectures; 2D array; 4-bit ALU; 4-bit barrel shifter; 4-bit registers; FIR filters; block-mode reconfiguration; coarse-grained configurable logic blocks; high-performance computational kernals; inverse DCT functions; local programmable control unit; on-chip memory; parallel multiply function; partial run-time reconfiguration; programmable high-speed clocks; reconfigurable array media processor; scalable parallel multiplier; Clocks; Finite impulse response filter; Logic arrays; Programmable control; Programmable logic arrays; Random access memory; Reconfigurable logic; Registers; Runtime; Video signal processing;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7695-0871-5
DOI :
10.1109/FPGA.2000.903420
