Title :
Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition
Author :
Kumar, B. Sandeep ; Pudi, Vikramkumar ; Sridharan, K.
Author_Institution :
Dept. of Elec. Eng., Indian Inst. of Technol. Madras, Chennai, India
Abstract :
We present efficient architectures for the discrete Hadamard transform based on two techniques, namely offset binary coding and ROM decomposition. The proposed architectures do not require large size ROMs in comparison to a recently proposed solution. Results of FPGA implementation show that the solutions have a low slice-delay product.
Keywords :
Hadamard transforms; VLSI; binary codes; discrete transforms; field programmable gate arrays; read-only storage; FPGA; ROM decomposition; VLSI architectures; discrete Hadamard transform; offset-binary coding; Computer architecture; Error correction; Error correction codes; Field programmable gate arrays; Read only memory; Transforms; Very large scale integration; Distributed Arithmetic; Hadamard Transform; Offset Binary Coding; ROM Decomposition; Slice-Delay Product;
Conference_Titel :
VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
Conference_Location :
Chennai
Print_ISBN :
978-1-4577-0803-9
Electronic_ISBN :
2159-3469
DOI :
10.1109/ISVLSI.2011.25
