Title :
Architectures for Simultaneous Coding and Encryption Using Chaotic Maps
Author :
Pande, Amit ; Zambreno, Joseph ; Mohapatra, Prasant
Author_Institution :
Dept. of Comput. Sci., Univ. of California, Davis, CA, USA
Abstract :
In this work, we discuss an interpretation of arithmetic coding using chaotic maps. We present a hardware implementation using 64 bit fixed point arithmetic on Virtex-6 FPGA (with and without using DSP slices). The encoder resources are slightly higher than a traditional AC encoder, but there are savings in decoder performance. The architectures achieve clock frequency of 400-500 MHz on Virtex-6 xc6vlx75 device.
Keywords :
cryptography; encoding; field programmable gate arrays; AC encoder; Virtex-6 FPGA; chaotic maps; coding; encryption; frequency 400 MHz to 500 MHz; word length 64 bit; Context modeling; Decoding; Encoding; Encryption; Hardware; Table lookup; Arithmetic coding; FPGA; encryption;
Conference_Titel :
VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
Conference_Location :
Chennai
Print_ISBN :
978-1-4577-0803-9
Electronic_ISBN :
2159-3469
DOI :
10.1109/ISVLSI.2011.14
