Multiple precision for resource minimization

Author

Constantinides, George A. ; Cheung, Peter Y K ; Luk, Wayne

Author_Institution

Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK

fYear

2000

fDate

2000

Firstpage

307

Lastpage

308

Abstract

Presents the Synoptix high-level synthesis and precision optimization system for FPGAs. Given abstract specifications in the form of infinite-precision signal flow graphs and a set of error constraints, Synoptix creates hardware descriptions of fixed-point arithmetic implementations. The width of each signal is individually optimized in order to achieve the minimal resource utilization while satisfying user-specified constraints such as signal-to-noise ratio. A heuristic for solving the optimization problem is introduced, and the results of implementations on an Altera Flex10k-based reconfigurable computing platform are reported. It is demonstrated that significant area reductions can be obtained by optimizing signal widths individually, compared to the use of a single uniform signal width

Keywords

field programmable gate arrays; high level synthesis; minimisation; reconfigurable architectures; resource allocation; signal flow graphs; Altera Flex10k-based reconfigurable computing platform; FPGA; Synoptix; abstract specifications; area reductions; error constraints; fixed-point arithmetic implementations; hardware descriptions; heuristic; high-level synthesis system; infinite-precision signal flow graphs; minimal resource utilization; multiple precision; precision optimization system; resource minimization; signal width optimization; signal-to-noise ratio; user-specified constraints; Adders; Circuits; Digital signal processing; Educational institutions; Field programmable gate arrays; Fixed-point arithmetic; Flow graphs; Hardware; High level synthesis; Minimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-7695-0871-5

Type

conf

DOI

10.1109/FPGA.2000.903430

Filename

903430