• DocumentCode
    2874254
  • Title

    Power-Efficient Inter-Layer Communication Architectures for 3D NoC

  • Author

    Rahmani, Amir-Mohammad ; Latif, Khalid ; Vaddina, Kameswar Rao ; Liljeberg, Pasi ; Plosila, Juha ; Tenhunen, Hannu

  • fYear
    2011
  • fDate
    4-6 July 2011
  • Firstpage
    355
  • Lastpage
    356
  • Abstract
    In this work, an efficient hybridization architecture to optimize power consumption and system performance of Hybrid NoC-Bus 3D mesh is proposed. Hybrid NoC-Bus 3D mesh is a feasible architecture which takes advantage of the short inter-layer wiring delays, while suffering from inefficient intermediate buffers. To address this issue, we propose a mechanism benefiting from a low-power congestion-aware routing algorithm for vertical communication. Our extensive simulations demonstrate significant power and performance improvements compared to a typical Hybrid NoC-Bus 3D architecture.
  • Keywords
    network routing; network-on-chip; three-dimensional displays; hybrid NoC-bus 3D mesh; interlayer wiring delays; low-power congestion-aware routing algorithm; power consumption; power-efficient interlayer communication architectures; Algorithm design and analysis; Computer architecture; Performance evaluation; Power demand; Routing; Three dimensional displays; Traffic control; 3D ICs; 3D NoC-Bus Hybrid Architecture; Fault Tolerance; Routing Algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Chennai
  • ISSN
    2159-3469
  • Print_ISBN
    978-1-4577-0803-9
  • Electronic_ISBN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2011.12
  • Filename
    5992543