Title :
Wafer mapping of bulk traps in silicon using scanning capacitance transient spectroscopy
Author :
Takahashi, Mitsuru ; Yoshida, Haruhiko ; Satoh, Shinichi
Author_Institution :
Hyogo Univ., Himeji, Japan
Abstract :
In this paper, we report a newly developed scanning capacitance transient spectroscopy (SCTS) that enables the electrical characterization of semiconductor wafers by contactless and nondestructive fashion. The validity of the developed system has been demonstrated using a partially Au-doped Si wafer.
Keywords :
ULSI; deep level transient spectroscopy; elemental semiconductors; gold; nondestructive testing; semiconductor device testing; semiconductor epitaxial layers; silicon; Si:Au; bulk traps; scanning capacitance transient spectroscopy; semiconductor wafers; wafer mapping; Capacitance measurement; Capacitance-voltage characteristics; Contacts; Electric variables measurement; Electrodes; Fabrication; Gold; Impurities; Silicon; Spectroscopy;
Conference_Titel :
Future of Electron Devices, 2004. International Meeting for
Print_ISBN :
0-7803-8423-7
Electronic_ISBN :
0-7803-8424-5
DOI :
10.1109/IMFEDK.2004.1566425
