A C to hardware/software compiler

Author

Bazargan, Kiarash ; Kastner, Ryan ; Ogrenci, Seda ; Sarrafzadeh, Majid

Author_Institution

Dept. of Electr. & Comput. Sci., Northwestern Univ., Evanston, IL, USA

fYear

2000

fDate

2000

Firstpage

331

Lastpage

332

Abstract

Improvements in FPGA technology have resulted in the introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. We present a top-down compilation method, under development, for such systems. We compile a C program into hierarchical VHDL source files, and annotate them with the placement information of the hardware modules to be configured on the FPGA. Static scheduling combined with a fast, two-stage placement core reduces the compilation time of large programs to minutes

Keywords

C language; field programmable gate arrays; hardware description languages; hardware-software codesign; program compilers; reconfigurable architectures; scheduling; C program; FPGA; hardware adaptation; hardware compiler; hierarchical VHDL source files; program compiler; reconfigurable computing machines; speedup; static scheduling; top-down compilation method; two-stage placement core; Application software; Coprocessors; Digital signal processing; Electronics packaging; Fabrics; Hardware; Libraries; Processor scheduling; Programming profession; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-7695-0871-5

Type

conf

DOI

10.1109/FPGA.2000.903440

Filename

903440