Title :
Asuka Project - mission and status
Author_Institution :
Semicond. Leading Edge Technol., Inc., Japan
Abstract :
An SoC device necessitating low power features has been increasingly significant for the coming information network society. On the other hand, the higher technology barrier (red brick wall in IRTS) has resulted in enormous R&D investment, so that the Japanese semiconductor manufacturers may collaborate with pre-competitive R&D tasks for the advanced SoC devices. On the basis of this background, this paper reports on development of the 65 nm node device process technologies in the ASUKA Project.
Keywords :
integrated circuit manufacture; low-power electronics; nanotechnology; research and development; system-on-chip; 65 nm; Asuka Project; Japanese semiconductor manufacturers; R&D; advanced SoC devices; device process technologies; low power features; technology barrier; Dielectric materials; Electron optics; High K dielectric materials; High-K gate dielectrics; Lithography; Optical films; Optical interconnections; Optical materials; Research and development; Resists;
Conference_Titel :
Future of Electron Devices, 2004. International Meeting for
Print_ISBN :
0-7803-8423-7
Electronic_ISBN :
0-7803-8424-5
DOI :
10.1109/IMFEDK.2004.1566437
