DocumentCode :
2874465
Title :
An investigation of reconfigurable multipliers for use in adaptive signal processing
Author :
Courtney, Timothy ; Turner, Richard ; Woods, Roger
Author_Institution :
Sch. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK
fYear :
2000
fDate :
2000
Firstpage :
341
Lastpage :
343
Abstract :
This paper looks at various XC6200 multiplier architectures for use within adaptive signal processing systems. It compares data throughput, block utilisation and reconfiguration times. A number of approaches are compared including fully programmable multipliers and three separate ways of implementing reconfigurable multipliers. The paper shows how fixed coefficient multipliers can be used to increase the number of multipliers from 4 to 10. Many of the ideas and rules can be extended to more recent fine grain architectures
Keywords :
adaptive signal processing; multiplying circuits; reconfigurable architectures; XC6200 multiplier architectures; adaptive signal processing; block utilisation; data throughput; fine grain architectures; fixed coefficient multipliers; fully programmable multipliers; reconfigurable multipliers; reconfiguration times; Adaptive signal processing; Circuits; Field programmable gate arrays; Hardware; Pipeline processing; Reconfigurable logic; Registers; Routing; Signal processing algorithms; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7695-0871-5
Type :
conf
DOI :
10.1109/FPGA.2000.903445
Filename :
903445
Link To Document :
بازگشت