Title :
Combining serialisation and reconfiguration for convolver designs
Author :
Derbyshire, Arran ; Luk, Wayne
Author_Institution :
Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK
Abstract :
This paper describes techniques for combining serialisation and reconfiguration to produce efficient convolver designs. Several optimisation techniques, such as restructuring and pipeline morphing, are presented with an analysis of their impact on performance and resource usage. The proposed techniques do not require the basic processing element to be modified. An estimate of the performance of a serial design is given when mapped using a distributed arithmetic core onto a Xilinx Virtex FPGA. We estimate that a convolver of more than 2000 taps at 470,000 samples per second can be implemented in one quarter of the logic resources of a Virtex XCV300 device
Keywords :
distributed arithmetic; feedback; field programmable gate arrays; performance evaluation; pipeline processing; Xilinx Virtez FPGA; convolver designs; distributed arithmetic core; logic resources; optimisation; performance; pipeline morphing; reconfiguration; resource usage; serial design; serialisation; Arithmetic; Convolvers; Delay; Educational institutions; Feedback; Field programmable gate arrays; Logic arrays; Logic devices; Performance analysis; Pipeline processing;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7695-0871-5
DOI :
10.1109/FPGA.2000.903446
