DocumentCode
2874543
Title
Synthesizable wide range DPWM with all-digital PLL for digitally-controlled switching converter
Author
Yang, Chun-Hung ; Mu, Chin-Wei ; Tsai, Chien-Hung
Author_Institution
Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
fYear
2011
fDate
7-10 Nov. 2011
Firstpage
1626
Lastpage
1630
Abstract
This paper proposes a synthesizable digital pulse-width modulator (DPWM) architecture, which combines conventional hybrid DPWM with all-digital phase-locked loop (ADPLL) schemes. The digitally controlled oscillator (DCO) of the ADPLL shares hardware with the delay line in the hybrid DPWM to reduce cost. The ADPLL allows the proposed DPWM to accurately calibrate its operating frequency (i.e., the switching frequency) to counteract the delay lines´ process, voltage, and temperature (PVT) effects in a wide frequency range. An FPGA prototype DPWM and its associated digitally controlled buck converter system are implemented to verify the proposed architecture.
Keywords
digital phase locked loops; field programmable gate arrays; oscillators; pulse width modulation; switching convertors; ADPLL; FPGA prototype DPWM; PVT effects; all-digital PLL; all-digital phase-locked loop; delay lines; digital pulse-width modulator; digitally controlled oscillator; digitally-controlled switching converter; synthesizable wide range DPWM; Clocks; Delay; Delay lines; Field programmable gate arrays; Mathematical model; Switching frequency;
fLanguage
English
Publisher
ieee
Conference_Titel
IECON 2011 - 37th Annual Conference on IEEE Industrial Electronics Society
Conference_Location
Melbourne, VIC
ISSN
1553-572X
Print_ISBN
978-1-61284-969-0
Type
conf
DOI
10.1109/IECON.2011.6119550
Filename
6119550
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