DocumentCode :
2874548
Title :
Body bias controlled SOI technology with HTI
Author :
Tsujiuchi, Mikio ; Hirano, Yuuichi ; Iwamatsu, Toshiaki ; Ipposhi, Takashi ; Maegawa, Shigeto ; Inuishi, Masahide ; Ohji, Yuzuru
Author_Institution :
Dept. of Adv. Device Dev., Renesas Technol. Corp., Hyogo, Japan
fYear :
2004
fDate :
26-28 July 2004
Firstpage :
131
Lastpage :
132
Abstract :
As the LSI process technology advances, increase of power consumption for the LSIs becomes major issue because of number of transistors and clock frequencies increase. For a reduction of the power consumption of the LSI, lowering supply voltage technology is one of the effective ways such as applying a dynamic threshold voltage (DT) structure as stated in J. P. Colinge (1987). However, a DT SOI MOSFET with T-shape or H-shape gates has disadvantages of area penalties and a gate parasitic capacitance increase. In this paper we describe actively body-bias controlled (ABC) SOI MOSFET technology with hybrid trench isolation (HTI) based in Y. Hirano et al. (2000). This structure doesn´t need the T or H gates and realizes low-voltage and high-speed operation with controlling a body potential.
Keywords :
MOSFET; isolation technology; large scale integration; low-power electronics; silicon-on-insulator; DT SOI MOSFET; LSI process technology; body-bias controlled SOI MOSFET; dynamic threshold voltage; high-speed operation; hybrid trench isolation; low-voltage operation; power consumption; supply voltage technology; Clocks; Energy consumption; Frequency; Inverters; Large scale integration; MOSFET circuits; Parasitic capacitance; Propagation delay; Threshold voltage; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Future of Electron Devices, 2004. International Meeting for
Print_ISBN :
0-7803-8423-7
Electronic_ISBN :
0-7803-8424-5
Type :
conf
DOI :
10.1109/IMFEDK.2004.1566443
Filename :
1566443
Link To Document :
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