Title :
Thin bonded wafer SOI CMOS technology for low voltage high performance applications
Author :
Nowak, E.D. ; Ding, L. ; Loh, Y.T. ; Hu, C.
Author_Institution :
University of California
Keywords :
CMOS process; CMOS technology; Circuit optimization; Delay effects; Low voltage; MOSFET circuits; Semiconductor films; Silicon on insulator technology; Threshold voltage; Wafer bonding;
Conference_Titel :
Electron Devices and Materials Symposium, 1994. EDMS 1994. 1994 International
DOI :
10.1109/EDMS.1994.771270
