Title :
An automatically designed 32b CMOS VLSI processor
Author :
Horiguchi, Shogo ; Yoshimura, Hiroyuki ; Kassai, R. ; Sudo, Toshio
Author_Institution :
Nippon Tel.-Tel. Musashino Electrical Communication Laboratory, Tokyo, Japan
Abstract :
A 32b CMOS VLSI processor chip designed automatically, including 17K gates of random logic and 2304b RAM will be described. Silicon gate technology offers an average loaded propagation delay of 1.6ns/gate using 2μm design rules.
Keywords :
Automatic logic units; CMOS logic circuits; CMOS process; CMOS technology; Logic design; Logic gates; Process design; Propagation delay; Silicon; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156372
