Title :
The future of high-speed logic in MOS, bipolar, GaAs, and Josephson junction ICs
Author_Institution :
Hewlett-Packard Co., Palo Alto, CA, USA
Abstract :
During the 80s, line widths and spaces will shrink by an order of magnitude, gate delays will decrease by a factor of 3-5, and devices per unit area will increase by at least an order of magnitude. These drastic improvements will have significant impact on systems approaches and capabilities, but will raise questions about manufacturability and product reliability. Panelists will assess approaches, projections, limitations and applications in the next decade.
Keywords :
CMOS logic circuits; Delay; Engineering management; Gallium arsenide; Josephson junctions; Large scale integration; Logic design; Logic devices; Research and development management; Silicon;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156375
