Title :
A storage-node-boosted RAM with word line delay compensation
Author :
Fujishima, Kenzaburo ; Shimotori, K. ; Ozaki, Hiroaki ; Nakano, T.
Author_Institution :
Mitsubishi Electronic Corp., Itami-shi, Japan
Abstract :
A dynamic RAM architecture, storing 1.7VDDfor ´1´ level in the cell without any boosted clocks and eliminating the word line delay by means of a pulsed cell plate, will be described.
Keywords :
Capacitance; Clocks; DRAM chips; Delay lines; Equivalent circuits; Propagation delay; Read-write memory; Signal detection; Variable structure systems; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156385
