DocumentCode
2875255
Title
An NMOS DRAM controller
Author
Bazes, M. ; Nadir, J. ; Perlmutter, D. ; Mantel, B. ; Zak, O.
Author_Institution
Intel Corp., Santa Clara, CA, USA
Volume
XXV
fYear
1982
fDate
10-12 Feb. 1982
Firstpage
72
Lastpage
73
Abstract
An NMOS controller, generating control signals for a DRAM, with programmable interfaces, dual-port configurations and error correction support, will be discussed. The chip has a worst case delay of 35ns and can drive 500pF loads.
Keywords
Circuits; Clocks; DRAM chips; Delay; Logic design; MOS devices; Microprocessors; Random access memory; Read-write memory; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1982.1156398
Filename
1156398
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